We've had quite a lot of events on the calendar lately! In case you missed it, check out VP of Marketing McKenzie Ross's field notes from embedded world!

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Impressions from the opening morning of Compute Express Link DevCon, courtesy of Mohith Haridoss. If you spot him at the event, please say hello!

Today’s the day! Will we see you at Compute Express Link DevCon?

Will we see you sporting one of these beauties at Compute Express Link DevCon next week? 👀

Don't miss your chance to attend! hubs.la/Q02t-Ch40

Great to see so many people here at DesignAndReuse.com IP-SoC Silicon Valley!

Stop by, say hello to Mohith Haridoss, and pick up a keyboard fidget toy!

See you tomorrow, April 25, at Hyatt Regency Santa Clara for DesignAndReuse.com IP-SoC Silicon Valley!

Conference talks get underway at 9:00 AM, and you can visit SmartDV's exhibit table on the Mezzanine throughout the day.

Snag your free registration here: hubs.la/Q02t-zVc0

We're looking forward to two events next week—both in Santa Clara, California:

Design & Reuse IP-SoC Silicon Valley
📆 April 25
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CXL DevCon (first event ever!)
📆 April 30 – May 1
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We hope to see a lot of IP enthusiasts there!

“Sure, I’ll send you that datasheet right away!” The Smarties have been working hard today here at #EW24 !

If jet lag is setting in and you’re feeling a bit restless in those #EW24 conference sessions, stop by SmartDV’s stand (4-570) to pick up a keyboard fidget keychain.

The IP you need for your next ASIC or FPGA is just a few keystrokes away! 🤓

It’s that time again! #EW24 exhibits open right now! 🔊

Nürnberg, thank you for the very warm welcome—27C/81F, to be precise! ☀️

Though the weather will cool off in the coming days, things are sure to heat up at the Messe once embedded world gets underway.

We can’t wait to see everyone at #EW24 tomorrow!

.embedded world opens in just one week! Our Smarties will be ready to welcome you to SmartDV's exhibit stand in Hall 4 – IC & IP Design Area.

Here's a little map to help you find us! 🗺️

Get the full details about the conference here: hubs.la/Q02rB0Ll0

The exhibit hall at @DVCon_US opens shortly! If you’re looking for #semIP , step right this way! 👀

Will we see you at @DVCon_US this week?

Stop by our exhibit booth to try the giant #katamino puzzle 🧩

Learn how SmartDV’s #designIP and #VIP can fit into your next chip 📲

Will we see you next week at DVCon U.S.? We're exhibiting and looking forward to catching up with other #semIP enthusiasts!

Event information and registration: hubs.la/Q02mtGz80

SmartDV Redoubles Focus on Customer Experience and IP Your Way bit.ly/3UOV7N9

#ICYMI : Last week’s Chiplet Summit in San Jose included a panel discussion called “Making Chiplets a Viable Market”

One of the key assumptions from the panel is that there will be many #UCIe variants due the changes in memory in #HPC , driven by #AI applications

More impressions from #ChipletSummit : Achronix VP Product Planning Nick Ilyadis discusses data acceleration solutions

SmartDV is at large again today at Chiplet Summit!

Subramani Kengari of Applied Materials shared a heterogenous scaling roadmap—potentially a way to keep up with Moore’s Law. Note the various levels of integration required, hence the need for an interoperability platform

Here’s a little visual representation of some of the cool content we’ve been checking out at DesignCon today 👀

#DesignCon #UCIe #chiplets #chipdesign