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[SystemVerilog] interface と function を組み合わせると便利ですよ、という話 qiita.com/taichi-ishitan… #Qiita いしたにより

SystemVerilogでFPGA使う本書きたいけど、TLのつよつよFPGAマンからマサカリ飛んできそう

A blog from Antmicro providing an update on the progress in open-source SystemVerilog / UVM support in Verilator - an open-source tool for the ASIC design space. bit.ly/3iCuYAE

The #Verible language server brings #SystemVerilog code editing support to popular editors and #IDEs such as VS Visual Studio Code, #Vim , Neovim, #Emacs , #SublimeText , #Kakoune & Kate. Read more for integration details: antmicro.com/blog/2023/02/i… CHIPSAlliance Google Sublime HQ KDE Community

Stay informed on the JavaScript ecosystem 👇👇👇

篠塚さんの「SystemVerilog超入門」の書籍化が決まったようです。
artgraphics.co.jp/technology.html

LRUの回路が複雑とか90年代の話やろ！ｗ 俺にはSystemVerilogとVerilatorがあるんだが？？？とかイキって実装してみたら全然複雑になった、カス

Released v1.11.5 which fixes Slang and Verilator not working in WSL marketplace.visualstudio.com/items?itemName…

Check Your Compatible Future ❤💔

#dvcon_us starts now with the battle of the #uvm configuration databases #systemverilog

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Open source is great, but for SystemVerilog simulation I gravitated towards xsim. Xsim, and Vivado in general, is so slow it's unbearable.
Then I tried ModelSim free from microchip.com and now have it integrated with cocotb.org, exciting stuff.

どっかに単精度浮動小数点数の加算と乗算のSystemVerilog落ちてないかな。

SystemVerilogには類似の表現が多くありますが、全く同じ意味とは限りません。例えば、'{4,4,4}と{4,4,4}とは意味が異なります。

VeeR (aka SweRV) EH1 RISC-V CPU SystemVerilog to C++ simulation model conversion with Yosys CXXRTL. 23MB cpp file
Compilation with clang++14: 104 seconds.
Compilation with g++11: stopped when it was still running 3 hours later.
g++ doesn't handle 130k lines of templates well.

Agnisys Inc. _definitely_ wins DVCon U.S. . I won this sweet JBL Clip4 speaker in their reeeally hard SystemVerilog quiz.

#TangNano1k from Sipeed with GOWIN SEMICONDUCTOR #FPGA controls stepper motor. Next tutorial on progress! #electronics #Robotic #diy #SystemVerilog

Just added XLS to the list of open source #SemiEDA tools, it produces Verilog and SystemVerilog output from a high level input. semiwiki.com/wikis/industry… #SemiWiki #SemiIP

Matt Harrison Basic
TI-85
Pascal
Java
C++
Perl
Bash/ksh
C
Python
Verilog
SystemVerilog

Have toyed with: emacs lisp, awk, Javascript, C#, SQL, probably others I don't remember

Want to learn/use: zig

Show HN: A High-Performance CRC Hardware Generator in Bluespec SystemVerilog ift.tt/FA605N2 ift.tt/yxGFVrB

次にあるかもしれない新刊
趣味のSystemVerilog入門

技術書典15に間に合わせたい
そしてこれがたぶん最後です

starting to treat 'SystemVerilog' not as a programming language with a specification, but as a shared universe that a bunch of writers used to write fiction in, and they sort of have the same idea in their heads and agree on the basics, but it gets very fuzzy near the edges

Valar Morghulis 我孙子•润二 verilog没人用了，现在都用SystemVerilog了，贼高级，OOP各种用法一应俱全🤪